This invention relates to digital computers, and more particularly microprocessors that are constructed on a single semiconductor chip. Typically, such microprocessors include an adder, a data memory, and an accumulator. These components are interconnected to perform various instructions that are stored in an instruction memory. For example, one instruction which practically all microprocessors perform is to pass data from the data memory and accumulator through the adder and back to the accumulator.
All of the microprocessors in the prior art also have some input/output or "I/O" registers. These allow the microprocessor to transmit information to and receive information from external devices. The I/O registers are loaded and unloaded under control of instructions from the instruction memory.
In the disclosed invention, the I/O register functions not simply as a means for transmitting and receiving information, but also as an external event counter. That is, it can be loaded with some initial value, and then can subsequently be incremented in response to an external signal.
In the prior art, many microprocessors do not provide this function at all. Further, those microprocessors that do provide an I/O register with incrementing capabitity utilize considerably more hardware than does the disclosed invention. For example, some microprocessors simply provide a second adder. This second adder receives inputs from the I/O register and the external signal and provides an output back to the I/O register. An alternative implementation would be to construct the I/O register of triggerable flip-flops which are interconnected to form a counter.
Both of these implementations however, require substantial amounts of hardware which in turn utilize corresponding amounts of space on the chip. And chip space is of course, at a premium. Thus, it is highly desirable to reduce the hardware and corresponding space that is required to implement an external event counter on a digital microprocessor chip.
Accordingly, it is one object of the invention to provide an improved microprocessor on a semiconductor chip.
Another object of the invention is to provide a microprocessor having an external I/O event counter that uses reduced hardware.